[01] Jin Li, School of Information and Electrical Engineering, Hunan University of Science and Technology, Xiangtan, China. [02] Shigang Hu, School of Information and Electrical Engineering, Hunan University of Science and Technology, Xiangtan, China. [03] Xiaofeng Wu, School of Information and Electrical Engineering, Hunan University of Science and Technology, Xiangtan, China. [04] Qingyang Wu, School of Information and Electrical Engineering, Hunan University of Science and Technology, Xiangtan, China. [05] Huiyi Cao, School of Information and Electrical Engineering, Hunan University of Science and Technology, Xiangtan, China.

In this paper, a new nanoscale graded channel (GC) gate stack (GS) double-gate (DG) strained-Si MOSFET structure and its two-dimensional analytical model have been proposed, An abrupt transition of strained-Si layer doping at the interface has been assumed and the effects of the doping and the lengths of the high and low doped regions have been taken into account. The model is used to obtain the expressions of surface potential and electric field in the two regions. The analysis is extended to obtain the expressions for threshold voltage (V_th), subthreshold current and subthreshold swing. It is shown that a graded doping profile in the channel leads to suppression of short- channel-effects (SCEs) like V_th roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. The results so obtained have been compared with simulated results obtained using the device simulator ISE-TCAD is found to be in good agreement.

Graded Channel, DG MOSFET, Short-Channel-Effects (SCEs), Hot Carrier Effects

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