[01] M. Salami, Faculty of Electrical and Computer Engineering, Hakim Sabzevari University, Sabzevar, Iran. [02] M. H. Shahrokh Abadi, Faculty of Electrical and Computer Engineering, Hakim Sabzevari University, Sabzevar, Iran.

A mathematical model of fully-depleted ultrathin silicon on insulator with buried oxide and four individual gates field effect transistor (G4-FDSOI-FET) has been developed to determine the effects of the oxide thickness as well as the channel width on the threshold voltage. Two dimensional Poisson’s equation has been carried out to model the device. The results show that the threshold voltage depends on the back surface conditions and is a function of structural parameters of oxide thicknesses of front and back gates as well as the width and thickness of the channel.

Fully Depleted, Multi-Gate, Threshold Voltage, Silicon on Insulator, MOSFET

[01] Rahou FZ, Bouazza AG, Rahou M. Electrical Characteristics Comparison Between Fully-Depleted SOI MOSFET and Partially-Depleted SOI MOSFET using Silvaco Software. Global Journal of Researches in Electrical and Electronics Engineering. 2013; 13: 1–6. [02] Fossum JG, Trivedi VP. Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs: Cambridge University Press; 2013. [03] Mazurier J, Weber O, Andrieu F, Toffoli F, Rozeau O. On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells. Electron Devices IEEE Transactions on. 2011; 58: 2326–2336. [04] Kumar, Tiwari PK. A Threshold Voltage Model of Short-Channel Fully-Depleted Recessed-Source/Drain (Re-S/D) UTB SOI MOSFETs Including Substrate Induced Surface Potential Effects. Solid-State Electronics. 2014; 95: 52–60. [05] Vitale SA, Wyatt PW, Checka N, Kedzierski J, Keast CL. FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics. Proceedings of the IEEE. 2010; 98: 333–342. [06] Ranka D, Rana AK, Yadav RK, Giri D. Performance Analysis of FD-SOI MOSFET with Different Gate Spacer Dielectric. International Journal of Computer Applications. 2011; 18: 22–27. [07] Fernandez C, Rodriguez N, Ohata A, Gamiz F. Bias-Engineered Mobility in Advanced FD-SOI MOSFETs. IEEE Electron Device Letters. 2013; 34: 840–842. [08] Sayed S, Hossain MI, Khan MZR. A Subthreshold Swing Model for Thin-Film Fully Depleted SOI Four-Gate Transistors. IEEE Transaction on Electron Devices. 2012; 59: 854–857. [09] Noor SL, Haq AFMS, Hassan M. Study of Threshold Voltage of p-channel Four Gate Transistor. Informatics, Electronics & Vision (ICIEV), IEEE International Conference on. 2013; 1–4. [10] Akarvardar K, Cristoloveanu S, Gentil P. Analytical Modeling of the Two-Dimensional Potential Distribution and Threshold Voltage of the SOI Four-Gate Transistor. IEEE Transactions on Electron Devices. 2006; 53: 2569–2577. [11] Sayed S, Hossain MI, Huq R, Khan MZR. Three Dimensional Modeling of SOI Four Gate Transistors. IEEE Nanotechnology Materials and Devices Conference. 2010; 383–388. [12] Sayed S, Khan MZR. Analytical Modeling of Surface Accumulation Behavior of Fully Depleted SOI Four Gate Transistors (G⁴-FETs). Solid-State Electronics. 2013; 81: 105–112.